A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. The high level behavior descriptions of the IC device are translated into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use EDA layout tools to create a physical integrated circuit design layout from a logical circuit design. The layout tools use geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools.
Optical lithography, which is also referred to as photolithography, is a fabrication process by which patterns for various devices are generated on substrate wafers. One or more photomask, or more simply “masks,” provide the master image of a layer of a given integrated circuit chip's physical geometries. A typical photolithography system projects UV light energy onto and through the one or more masks in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer.
The resolution limit of conventional optical lithography technology is increasingly being challenged by the sub wavelength dimensions of the critical IC feature dimensions and geometries. Not only are the critical dimension feature geometries steadily decreasing in size, but the quantity of these features is also growing at a dramatic rate as well. These critical feature geometries also need to be patterned very precisely due to the severity and sensitivity of the imaging process. Extreme precision is required for sub wavelength, or low-kl, applications due to highly non-linear imaging behaviors which often magnify mask errors by large factors and in non-intuitive manners.
For at least these reasons, designers are increasingly aggressive in their use of artificial layout enhancement for manufacturability (LEM) features such as Resolution Enhancement Technology (RET) and Optical Proximity Correction (OPC). These are usually in the form of mask data manipulation which counter the effects of the modeled behavior of the entire lithography process.
To illustrate how OPC may be advantageously used to enhance the resolution of a manufactured layout, consider the example layout portion shown in FIG. 1. This layout portion includes a first feature 102 in an end-to-end configuration relative to a second feature 106. The two features 102 and 106 are separated by distance 112, where the distance 112 significantly exceeds critical dimension thresholds for the layout.
Due to well understood optical lithographic effects, it is highly unlikely that features 102 and 106 will end up lithographically printed as regular rectangular shapes having the exact position and exact shape (e.g., sharp corners) of the patterns shown in the original layout. In fact, it is quite likely that all of the sharp corners of the original layout patterns will be smoothed away leaving rounded corners and non-straight edges. It is also quite likely that the location and dimensions of the resultant printed shapes will shift a considerable distance from the original layout pattern locations.
A possible example of a printed shape for feature 102 is shown as shape 104a. A possible example of a printed shape for feature 106 is shown as shape 108a. It is noted that the location of the printed shapes in this example has varied from the original location of the layout features 102 and 106. For example, the extended end of printed shape 104a does not quite reach the original position of the edge of the feature 102, but instead varies by a distance 110 away from the original edge of feature 102. Moreover, the end of the shape 104a has an excessively rounded appearance that is significantly narrower than the width of the original feature 102. The dimensional and location-related variances between the actually printed shape 104a and the original rectangular layout feature 102 may result in performance or yield problems for the final IC product.
To address these problems, an EDA tool may apply OPC processing to modify the existing layout or add new features to the layout to provide enough bias such that the lithographically printed shapes will more closely match the desired shape, location, and dimensions of the desired layout features. For example, OPC processing may be used to add hammerhead patterns 114 and 116 to features 102 and 106, respectively. If the OPC structures 114 and 116 are properly configured, the printed shapes 104b and 108b will have their end edges substantially match the location of the end edges of the features 102 and 106. In addition, the width of the end portions of printed shapes 104b and 108b will substantially approach the width of the features 102 and 106.
In the example of FIG. 1, the designer was fortunate enough to have sufficient space between the two features 102 and 106 to add the required OPC structures. However, with many modern IC designs, it is quite likely that layout objects are placed with very little available space between features. There is usually a limit on how small or close the lines and spaces can be based on the process capability. In many cases, particularly for the common configuration having line end to line end, the limited space between the features will also limit how and how much RET is available and therefore limit the ability to address allowable line end shortening (LES).
To illustrate this problem, consider the example layout portion shown in FIG. 2. This layout portion includes a first feature 202 in an end-to-end configuration relative to a second feature 206. Here, the two features 202 and 206 are separated by a very small distance 212, where the distance 212 significantly corresponds to critical dimension thresholds for the layout.
Without OPC processing, the lithographically printed shapes 204a and 208a have dimensions, locations, and shapes that substantially vary from the intended dimensions, locations, and shapes of the original layout features 202 and 206. For example, the extended end of printed shape 204a does not quite reach the original position of the edge of the feature 202, where the printed shape 204a varies by a distance 210a away from the original edge of feature 202. In addition, the end of the printed shape 204a has an excessively sharpened and rounded appearance that is significantly narrower than the width of the original feature 202.
OPC may be applied to correct some of these printing issues. For example, OPC structures 214 and 216 may be added to the layout to bias the end-width of the printed shapes 204b and 208b such that the ends of the printed shapes 204b and 208b appear more rectangular and have a width that more closely approximates the width of the original features 202 and 206.
However, there is insufficient spacing between the features 202 and 206 to allow conventional OPC processing to significantly bias the ends of printed shapes 204b and 208b towards each other because of mask rule constraints. As such, even after conventional OPC processing is applied, the ends of printed shapes 204b and 208b suffer from significant line end shortening.
As is evident, there is a need for improved approaches to address and correct for the shortcomings of conventional RET and OPC processing.
Some embodiments of the present invention provide a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.